A storage capacity of a semiconductor memory device represented by a DRAM (Dynamic Random Access Memory) has yearly increased and there is a demand for acceleration of the semiconductor memory device. To realize high-speed operation of the DRAM, it is essential to accelerate the speed of a sense amplifier that amplifies a potential difference between a pair of bit lines.
To accelerate the sense speed of the sense amplifier, it is preferable to provide a transfer gate between a bit line of cells and the sense amplifier and to thus make the sense amplifier perform sense operation while not connecting the bit line of the cells to the sense amplifier but separating the cells from the sense amplifier. By doing so, the capacity by which the sense amplifier is to charge or discharge is reduced, so that the sense speed can be accelerated.
On the other hand, due to recent development of miniaturization, the influence of coupled noise between bit lines in the sense amplifier has increased to a level that is no longer negligible. To reduce the coupled noise, the following method is proposed. The bit lines of the sense amplifier, i.e., the paired bit lines located on the sense amplifier side relative to the transfer gate are twisted, thereby canceling the coupled noise.
FIG. 8 is a circuit diagram showing relevant parts of a semiconductor memory device in which the bit lines of the sense amplifier are twisted.
The semiconductor memory device shown in FIG. 8 includes a sense amplifier 10, a first pair of bit lines 21 and 22, a second pair of bit lines 31 and 32. The sense amplifier 10 includes a first input/output terminal 11 and a second input/output terminal 12. The first pair of bit lines 21 and 22 is provided on one side of the sense amplifier 10. The second pair of bit lines 31 and 32 is provided on the other side of the sense amplifier 10. The bit line 21 included in the first pair of bit lines and the bit line 31 included in the second pair of bit lines are connected to the first input/output terminal 11 of the sense amplifier 10 in common. The bit line 22 included in the first pair of bit lines and the bit line 32 included in the second pair of bit lines are connected to the second input/output terminal 12 of the sense amplifier 10 in common.
The sense amplifier 10 has a function of amplifying a potential difference generated between the first and the second input/output terminals 11 and 12. Therefore, the relationship between logic values of the bit lines 21 and 31 connected to the first input/output terminal 11 and a physical level is opposite to that between logic values of the bit lines 22 and 32 connected to the second input/output terminal 12 and a physical level. Due to this, if the bit lines 21 and 31 are defined as “non-inverted bit lines”, the bit lines 22 and 32 can be defined as “inverted bit lines”.
The first pair of bit lines 21 and 22 is connected to the sense amplifier 10 through first and second transfer gates 41 and 42, respectively. The second pair of bit lines 31 and 32 is connected to the sense amplifier 10 through third and fourth transfer gates 43 and 44, respectively. The first and the second transfer gates 41 and 42 are turned on or off in response to a same signal T0 whereas the third and the fourth transfer gates 43 and 44 are turned on or off in response to a same signal T1.
As shown in FIG. 8, the first pair of bit lines 21 and 22 is connected to the sense amplifier 10 without being twisted with each other between the transfer gates 41 and 42 and the sense amplifier 10. On the other hand, the second pair of bit lines 31 and 32 is connected to the sense amplifier 10 while being twisted with each other between the transfer gates 43 and 44 and the sense amplifier 10. Due to this, the positional relationship between the bit lines 21 and 22 (the positional relationship between the non-inverted bit line and the inverted bit line) is opposite to that between the bit lines 31 and 32 (the positional relationship between the non-inverted bit line and the inverted bit line).
The twisted portion is provided to cancel the coupled noise between the bit lines in the sense amplifier (between the transfer gates 41 and 42 and the transfer gates 43 and 44).
However, if the twisted portion is provided, the first pair of bit lines 21 and 22 differs from the second pair of bit lines 31 and 32 in address data topology, which disadvantageously complicates the address data topology of the overall semiconductor memory device.
Specifically, when attention is paid to two word lines 51 and 52 intersecting the first pair of bit lines 21 and 22 and two word lines 53 and 54 intersecting the second pair of bit lines 31 and 32, memory cells 61 and 63 are arranged at the intersection between the upper bit lines 21 and 32 with respect to the word lines 51 and 53, while memory cells 62 and 64 are arranged at the intersection between the lower bit lines 22 and 31 with respect to the wordlines 52 and 54. As a result, although being arranged at positions corresponding to each other, the memory cells 61 and 63 (62 and 64) store therein the same logic value at different physical levels (potentials). For example, if it is necessary to store a logic value “1” in the memory cell 61 and store a high-level potential in the memory cell 61, it is necessary to store a low-level potential in the memory cell 61 when the memory cell 63 stores therein the logic value “1”.
There is no need for a user to recognize such complication of the address data topology when the user actually uses the semiconductor memory device. However, if a screening test for which it is necessary to actually recognize physical levels stored in the respective memory cells is conducted, a function exceeding the limit of the function of a tester for the screening test is often required. As a result, a conventional tester sometimes cannot be used for the test.
This disadvantage is conspicuous particularly if the number of memory cells connected to the first pair of bit lines 21 and 22 or the second pair of bit lines 31 and 32 differs from nth power of 2. This disadvantage will be described below.
As shown in FIG. 9, a memory mat including 1024 (=210) word lines will be considered. If the memory mat is divided into two plates 111 and 112, 512 (=29) word lines are allocated to each of the plates 111 and 112. In this case, the number of sense amplifier columns SAs is three. If one memory mat is divided into two plates, the length of each bit line is halved and read operation can be, therefore, accelerated.
To further accelerate the read operation, a memory mat including 1024 (=210) word lines is divided into four plates 111 to 114 as shown in FIG. 10. In this case, the number of word lines allocated to each plate is 256 (=28), thereby further reducing the length of each bit line. However, if the memory mat is divided into four plates, the number of sense amplifier columns SAs increases to five, thereby disadvantageously deteriorating integration.
In this way, if the memory mat is divided into a plurality of plates, the read operation can be accelerated due to reduction in the length of each bit line, but at the same time, the integration deteriorates due to increase in the number of sense amplifier columns SAs. Considering this point, it is quite often optimum to set the number of word lines allocated to each plate to the nth power of 2 (=2n) so as to simultaneously realize acceleration and high integration. In this case, as shown in FIG. 11, it is often necessary to divide a memory mat into, for example, three plates 111 to 113. If the memory mat is divided into the three plates 111 to 113, the numbers of word lines allocated to the respective plates are 344, 336, and 344, which differ from the nth power of 2.
If the numbers of word lines allocated to the respective plates differ from the nth power of 2, the boundary of a row address ranging over the sense amplifiers disadvantageously becomes unclear. Namely, if the number of word lines allocated to each plate is the nth power of 2 (see FIGS. 9 and 10), it is possible to easily grasp to which plate a row address corresponds by referring only to a few high bits of the row address. As a result, even if the address data topology is slightly complicated, it is not so difficult to conduct a screening test or the like by considering the complicated address data topology.
More specifically, as shown in FIG. 9, if the number of word lines allocated to each plate is 512 (=29), each plate can be identified without the need to refer to lower nine bits of the row address. Furthermore, as shown in FIG. 10, if the number of word lines allocated to each plate is 256 (=28), each plate can be identified without the need to refer to lower eight bits of the row address. As a result, as shown in FIG. 8, even if the address data topology is slightly complicated due to the twisted bit lines, it is not so difficult to correct the address data topology using the tester.
On the other hand, if the number of word lines allocated to each plate is not the nth power of 2 as shown in FIG. 11, it is necessary to refer to not only a few high bits but also many low bits of the row address so as to identify each plate. As a result, it is difficult to correct the complicated address data topology due to the twisted bit lines using the tester. For these reasons, if the number of word lines allocated to each plate is not the nth power of 2, i.e., if the number of memory cells connected to the first pair of bit lines 21 and 22 or the second pair of bit lines 31 and 32 shown in FIG. 8 differs from the nth power of 2, then the complicated address data topology due to the twisted bit lines greatly affects the screening test or the like, and it is sometimes necessary to employ a new tester.